`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2022/01/04 01:34:09
// Design Name: 
// Module Name: branch_judge
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module branch_judge(
    input wire[31:0] a,//rs
    input wire[31:0] b, //rt
    input wire[3:0] control_branch,
    output reg is_branch
    );
    
    always @(*)begin
       case(control_branch)
                4'b0101: begin  //BNE 
                    if(a!=b)begin
                        is_branch <=1'b1;
                    end else begin
                        is_branch <= 1'b0;
                        end
                end 
                4'b0100: begin //BGEZ 
                    if(a>=0)begin
                        is_branch <= 1'b1;
                    end else begin
                        is_branch <= 1'b0;
                        end
                end 
                4'b0011: begin  //BGTZ 
                    if(a>0) begin
                        is_branch <= 1'b1;
                    end else begin
                        is_branch <= 1'b0;
                        end
                end 
                4'b0010: begin  //BLEZ 
                    if(a<=0)begin
                        is_branch <=1'b1;
                    end else begin
                        is_branch <= 1'b0;
                        end
                end 
                4'b0001: begin //BLTZ 
                    if(a<0) begin
                        is_branch <= 1'b1;
                    end else begin
                        is_branch <= 1'b0;
                        end
                end
                4'b0110: begin //BEQ 
                    if(a==b)begin
                        is_branch <= 1'b1;
                    end else begin
                        is_branch <= 1'b0;
                        end
                end 
                4'b0111: begin  //BLTZAL
                    if(a<0)begin
                        is_branch <= 1'b1;
                    end else begin
                        is_branch <=1'b0;
                        end
                end 
                4'b1000: begin //BGEZAL
                    if(a[31] == 0) begin
                        is_branch <= 1'b1;
                    end else begin
                        is_branch <= 1'b0;
                        end
                end
                default: is_branch<=1'b0;
            endcase
    end
endmodule
